library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- A Programmable DIVN counter
--Created by Arun Kumar
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--Divides by  2,4,8,16,64,128

entity DIVN_CNTR is
   Port ( reset:in std_logic;
			 N :in std_logic_vector (6 downto 0);
	       DCO_CLK_IN: in STD_LOGIC;
		    DCO_CLK : out std_logic);
end DIVN_CNTR;


architecture Behavioral of DIVN_CNTR is


signal count: std_logic_vector (6 downto 0):= (others=>'0');
begin



process(reset,DCO_CLK_IN)
begin
if(reset = '1') then
	count <= conv_std_logic_vector(0,7);
	--DCO_CLK <= '0';
else
if(DCO_CLK_IN = '1' and DCO_CLK_IN'event) then
	if(count = conv_std_logic_vector(127,7)) then
			count <= conv_std_logic_vector(0,7);
	else
			count <= count + 1;
   end if;
end if;
end if;


case N is
when "0000001" =>
						DCO_CLK<=count(0);
when "0000010" =>
						DCO_CLK<=count(1);
when "0000100" =>
						DCO_CLK<=count(2);
when "0001000" =>
						DCO_CLK<=count(3);
when "0010000" =>
						DCO_CLK<=count(4);
when "0100000" =>
						DCO_CLK<=count(5);
when "1000000" =>
						DCO_CLK<=count(6);
when	others => DCO_CLK<= '0';
end case;
end process;


end behavioral;


